Semiconductor device

ABSTRACT

The semiconductor device includes a gate insulator with a three-layer stacked structure including a first insulator on a semiconductor substrate, a second insulator on the first insulator, and a third insulator on the second insulator. The first insulator is made of silicon oxide, silicon nitride, or oxinitrided silicon. The second and the third insulator contain a metal. The dielectric constant of the second insulator is higher than the square root of the product of the dielectric constants of the first and the third insulator. The present invention provides a high-speed semiconductor device, decreasing scattering of the carriers.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromprior Japanese Patent Applications P2003-313093 filed on Sep. 4, 2003;the entire contents of which are incorporated by reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device.

2. Description of the Related Art

With the aim to increase the operation speed of conventionalfield-effect transistors, a gate electrode is made of a refractory metalfor reducing resistance, and a gate insulator film is made of a highdielectric material for increasing current driving force. It is knownthat if the gate insulator film is made of a material such as a metaloxide, the mobility of carriers for carrying current through a channeldecreases compared to when the gate insulator film is made of siliconoxide. This lowers the current driving force and the device operationspeed, preventing high-speed operations of the device. This problem alsorequires attention when using a metal-containing material for the gateinsulator film (for example, JP, A (Japanese Patent ApplicationLaid-Open) No. 2003-8011).

When the gate insulator film is made of a material such as a metaloxide, the decrease in mobility is understood to emanate from the amountof charge existing at the interface between the gate insulator film anda semiconductor substrate or in the gate insulator film. In such a case,the charge is greater than when the gate insulator film is made ofsilicon oxide, and scattering of carriers moving through a channel isincreased as a result thereof. A structure providing a silicon oxidefilm or the like between the gate insulator film made of a material suchas a metal oxide and the semiconductor substrate has also beenconsidered. With such structure, there is little charge at the interfacebetween the gate insulator film and the semiconductor substrate sincethe insulator film in direct contact with the semiconductor is a siliconoxide film or the like. However, since an interface exists between thesilicon oxide film and the metal oxide insulator film in the devicestructure, charges also exist at that interface. The charges existing ina metal oxide insulator film or the like is also a problem. Therefore,scattering of the carriers due to the charges existing within theinsulator film cannot be reduced. On such basis, with a device using ahigh dielectric material such as a metal oxide for the gate insulatorfilm, the mobility of the carriers, which carry current through thechannel, is less than that with a device using silicon oxide for thegate insulator film. This prevents high-speed operations, especiallywhen using a metal-containing material for the gate insulator film.Furthermore, since the dielectric constant for silicon oxide is not veryhigh, provision of a silicon oxide layer between a metal oxide insulatorfilm or the like and the semiconductor substrate is equivalent to aconsiderable increase in the gate insulator film thickness. This weakensthe capacitive coupling between a channel region and a gate electrode,thus weakening the controllability of the gate electrode with respect tothe potential of the channel region. As a result, the resistance to theshort channel effect is reduced so as to prevent device miniaturization.Such phenomenon prevents implementation of high-speed operations.

The present invention is developed in order to solve the above problems,and provides a minute semiconductor device capable of high-speedoperations by reducing the scattering of carriers as well as enhancingthe controllability of the gate electrode with respect to the potentialof the channel region.

SUMMARY OF THE INVENTION

An aspect of the present invention inheres in a semiconductor device,including a semiconductor substrate; a source and a drain region, whichare arranged at the surface of the semiconductor substrate; a gateinsulator film, which is arranged on a channel defined between thesource and drain regions at the surface of the semiconductor substrateand is implemented by a stacked structure including a first insulatorfilm, a second insulator film containing a metal is provided on thefirst insulator film, and a third insulator film containing a metal isprovided on the second insulator film. A gate electrode is arranged onthe third insulator film, wherein the dielectric constant of the secondinsulator film is higher than the square root of the product of thedielectric constants of the first and third insulator films.

Another aspect of the present invention inheres in a semiconductordevice, including a semiconductor substrate; a source and a drain regionarranged at the surface of the semiconductor substrate. A gate insulatorfilm is arranged on a channel defined between the source and drainregions at the surface of the semiconductor substrate and is implementedby a stacked structure including a first insulator film containing ametal and a second insulator film containing a metal on the firstinsulator film. A gate electrode is arranged on the second insulatorfilm, wherein the dielectric constant of the first insulator film ishigher than the square root of the product of the dielectric constantsof the semiconductor substrate and the second insulator film.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram for describing a semiconductor device of anembodiment;

FIG. 2 is a block diagram for describing the semiconductor device of theembodiment;

FIG. 3 is a block diagram for describing the semiconductor device of theembodiment;

FIG. 4 is a cross section for describing the structure of a field-effecttransistor according to a first embodiment of the present invention;

FIG. 5 is a cross section for explaining a fabrication step for thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 6 is a cross section for explaining a fabrication step for thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 7 is a cross section for explaining a fabrication step for thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 8 is a cross section for explaining a fabrication step for thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 9 is a cross section for explaining a fabrication step for thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 10 is a cross section for explaining a fabrication step for thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 11 is a cross section for explaining a fabrication step for thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 12 is a cross section for explaining a fabrication step for thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 13 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 14 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 15 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 16 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 17 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 18 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 19 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 20 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 21 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 22 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 23 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 24 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 25 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 26 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 27 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 28 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 29 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 30 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 31 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 32 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 33 is a cross section for describing the modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 34 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 35 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 36 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 37 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 38 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 39 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 40 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 41 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 42 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 43 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 44 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 45 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 46 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 47 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 48 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 49 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 50 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 51 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 52 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 53 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 54 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 55 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 56 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 57 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 58 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 59 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 60 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 61 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 62 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 63 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 64 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 65 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 66 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 67 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 68 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 69 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 70 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 71 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 72 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 73 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 74 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 75 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 76 is a cross section for describing a modified example of thefield-effect transistor according to the first embodiment of the presentinvention;

FIG. 77 is a cross section for describing the structure of afield-effect transistor according to a second embodiment of the presentinvention;

FIG. 78 is a cross section for explaining a fabrication step for thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 79 is a cross section for explaining a fabrication step for thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 80 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 81 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 82 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 83 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 84 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 85 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 86 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 87 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 88 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 89 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 90 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 91 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 92 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 93 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 94 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 95 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 96 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 97 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 98 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 99 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 100 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 101 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 102 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 103 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 104 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 105 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 106 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 107 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 108 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 109 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 110 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 111 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 112 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 113 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 114 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 115 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 116 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 117 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 118 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 119 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 120 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 121 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 122 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 123 is a cross section for describing a modified example of thefield-effect transistor according to the second embodiment of thepresent invention;

FIG. 124 is a cross section of a field-effect transistor of acomparative example; and

FIG. 125 is a cross section of the field-effect transistor of anothercomparative example.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various embodiments of the present invention will be described withreference to the accompanying drawings. It is to be noted that the sameor similar reference numerals are applied to the same or similar partsand elements throughout the drawings, and the description of the same orsimilar parts and elements will be omitted or simplified.

Generally, and as is conventional in the representation of the devicestructure, it will be appreciated that the various drawings are notdrawn to scale from one figure to another nor inside a given figure, andin particular that the device cross-sectional diagrams are arbitrarilydrawn for facilitating the reading of the drawings.

In the following descriptions, numerous specific details are set forthto provide a thorough understanding of the present invention. However,it will be obvious to those skilled in the art that the presentinvention may be practiced without such specific details. In otherinstances, well-known device structures have been shown incross-sectional form in order to not obscure the present invention withunnecessary detail.

Referring to the drawings, embodiments of the present invention aredescribed below. The same or similar reference numerals are attached toidentical or similar parts among the following drawings. The embodimentsshown below exemplify a device structure and a fabrication method thatare used to implement the technical ideas according to the presentinvention, and do not limit the technical ideas according to the presentinvention to those that appear below. These technical ideas, accordingto the present invention, may receive a variety of modifications thatfall within the claims.

COMPARATIVE EXAMPLE

FIGS. 124 and 125 are cross sections of a field-effect transistor of acomparative example. An n-channel field-effect transistor is taken as anexample in this case.

As shown in FIGS. 124 and 125, the field-effect transistor of thecomparative example includes device isolation regions 2 formed on ap-type Si substrate 1 by trench device isolation. A p-well region 3 isformed in the p-type Si substrate through boron (B) ion implantation andthermal treatment, and an n-channel region 4 is formed in the p-wellregion 3 through B ion implantation.

In FIG. 124, a gate insulator film 5 such as a metal oxide with a higherdielectric constant than silicon oxide, is formed on the n-channelregion 4, and a gate electrode 6 is formed on the gate insulator film 5by depositing a 100 nm-thick refractory metal by sputtering.Furthermore, source/drain regions 7 are formed through arsenic (As) ionimplantation. Reference numeral 8 denotes interconnects, and 9 denotesinter-layer insulator films.

Furthermore, a device is shown in FIG. 125 with a gate insulator filmconfigured of stacked layers of a silicon oxide film 10 made of siliconoxide or oxidized and nitrided silicon provided between the gateinsulator film 5 made of a material such as a metal oxide and thesemiconductor substrate 1.

(First Embodiment)

In a field-effect transistor of this embodiment, a gate insulator filmis made of multiple stacked layers with differing dielectric constants.The dielectric constants are set as described above to suppressscattering of carriers due to charges in each layer or at the interfacesthereof. This is described forthwith. Stacked insulator films as shownin FIG. 1 are considered. FIG. 1 shows a structure of a first insulatorfilm 21, a second insulator film 22, a third insulator film 23, a fourthinsulator film 24, and a fifth insulator film 25 sequentially stackedand formed upon a semiconductor substrate 20. A semiconductor is on thebottom layer with a dielectric constant of ε_(Si). Furthermore,thickness of the bottom layer is not limited with regard to the effectof the reverse side of the side shown in the drawings. The insulatorfilms are stacked upon the semiconductor, where the j-th insulator film,counting from the bottom, has a dielectric constant ε_(j) and thicknessT_(j)(j=1, 2, . . . ). The potential within the semiconductor in thecase where a single point charge of size Q exists at the interfacebetween the n−1-th layer and the nth layer of these stacked insulatorfilms is considered. It is assumed that there is no charge in theinsulator films or the semiconductor other than Q. In addition, it isassumed that all interfaces are parallel to each other, and thedistribution along those parallel interfaces other than point charge Qis uniform.

The potential in the semiconductor along those interfaces may becalculated through the Fourier transform given below: $\begin{matrix}{\frac{Q\quad{\exp\left( {{- k}{{z - {\sum\limits_{l = 1}^{n - 1}\quad T_{l}}}}} \right)}}{2ɛ_{0}k}\left( {\prod\limits_{l = 0}^{n - 1}\quad\frac{2ɛ_{1}}{ɛ_{l + 1} + ɛ_{l}}} \right)\frac{B}{A}} & (1)\end{matrix}$where k denotes the wavenumber for the Fourier transform, and for thesake of convenience, the dielectric constant of the semiconductorcorresponding to ε_(Si) is given as ε₀ in Expression (1). Furthermore, Aand B are given as follows: $\begin{matrix}{A = {1 + {\sum\limits_{N \geq j > i \geq 0}\left\{ {E_{j}E_{i}{\prod\limits_{l = {i + 1}}^{j}{\exp\left( {{- 2}{kT}_{l}} \right)}}} \right\}} + {\sum\limits_{N \geq m > l > j > i \geq 0}{\left\{ {E_{m}E_{l}{\prod\limits_{p = {l + 1}}^{m}{\exp\left( {{- 2}{kT}_{p}} \right)}}} \right\}\left\{ {E_{j}E_{i}{\prod\limits_{r = {i + 1}}^{j}{\exp\left( {{- 2}{kT}_{r}} \right)}}} \right\}}} + \cdots}} & (2) \\{B = {1 + {\sum\limits_{N \geq j > i \geq {n - 1}}\left\{ {F_{j}F_{i}{\prod\limits_{l = {i + 1}}^{j}{\exp\left( {{- 2}{kT}_{l}} \right)}}} \right\}} + {\sum\limits_{N \geq m > l > j > i \geq {n - 1}}{\left\{ {F_{m}F_{l}{\prod\limits_{p = {l + 1}}^{m}{\exp\left( {{- 2}{kT}_{p}} \right)}}} \right\}\left\{ {F_{j}F_{i}{\prod\limits_{r = {i + 1}}^{j}{\exp\left( {{- 2}{kT}_{r}} \right)}}} \right\}}} + \cdots}} & (3)\end{matrix}$where N denotes the total number of insulator film layers minus one, andE_(i) and F_(i) (i=0, 1, . . . , N) are given as follows:$\begin{matrix}{E_{i} = \frac{ɛ_{i + 1} - ɛ_{i}}{ɛ_{i + 1} + ɛ_{i}}} & (4) \\{F_{i} = \left\{ \begin{matrix}E_{i} & \left( {i \neq {n - 1}} \right) \\{- 1} & \left( {i = {n - 1}} \right)\end{matrix} \right.} & (5)\end{matrix}$By substituting these expressions for Expression (1) and expanding 1/Λ,the Fourier transform of the potential in the semiconductor isrepresented by the power series exp (−kT_(j)) (j=1, 2, . . . ). Thewavenumber for the Fourier transform is denoted by k, as describedabove. Considering actual scattering of carriers, contribution of theFermi wavenumber, when the carriers in an inversion layer are regardedas a two-dimensional gas, is large. Here, considering the definitions ofE_(i) and F_(i) (i=0, 1, . . . , N), the respective absolute valuesthereof are understood to be no greater than 1. The principal term isthen extracted from that power series noting that exp(−kT_(j)) (j=1, 2,. . . ) is generally small. Only the principal term relevant to A and Bat the right side of Expression (1) should be considered. Consideringthe expressions of A and B, the principal term is equivalent to A=B=1.By extracting the principal term in this manner and subjecting it to theFourier inverse transform, the potential in the semiconductor is thesame as that when supposing that the entire space of medium is filledwith a material with dielectric constant ε_(Si), and is the same as thepotential where a point charge of a size given by the followingexpression exists at the position of Q.(2ε_(Si)(ε_(Si)+ε₁))×(2ε₁/(ε₁+ε₂))× . . .×(2ε_(n−1)/(ε_(n−1)+ε_(n)))×Q  (6)

It should be noted that the point charge Q exists at the interfacebetween the n−1-th layer and the nth layer of the stacked insulatorfilms in this case; however, in the same way as when Q exists in the nthlayer, the potential in the semiconductor is the same as in the casewhere the entire space of medium is filled with a material withdielectric constant ε_(Si), and a point charge of a size given byExpression (6) exists at the same position as Q. This can be understoodfrom the fact that if ε_(n−1) and ε_(n) are assumed to be equal in FIG.1, the point charge Q can be regarded to exist in the n−1-th layer, andthat the last term (2ε_(n−1)/(ε_(n−1)+ε_(n))) appearing in the productof Expression (6) in that case is equal to 1, and the product value isequal to the value of Expression (6) when substituting n−1 for n inExpression (6). Here, since the mobility of the carriers moving in thesemiconductor is inversely proportional to the scattering probability,and the scattering probability, which is determined by the chargesexisting within the gate insulator film and the interface between thegate insulator film and the semiconductor substrate, is proportional tothe square of the potential created by the existing charges, the smallerthe value of Expression (6), the greater the mobility of the carriers.

Here, a gate insulator film with at least three layers as shown in FIG.2 is considered. The insulator film closest to the semiconductorsubstrate is assumed to be a silicon oxide, silicon nitride, or oxidizedand nitrided silicon, and the third insulator film counting from thesemiconductor substrate is assumed to be an insulator film made of ahigh dielectric material, such as a metal oxide. The potentialdetermined by a charge Q1 existing in the third insulator film countingfrom the semiconductor substrate and a charge Q2 existing at theinterface between the second insulator film and the third insulator filmcounting from the semiconductor substrate is considered. This potentialis proportionate to(2 ε_(Si)/(ε_(Si)+ε₁))×(2ε₁/(ε₁+ε₂))×(2 ε₂/(ε₂+ε₃))  (7)when referencing Expression (6) and the description thereafter.Reduction in the value of Expression (7) by adjusting the dielectricconstant of the second insulator film counting from the semiconductorsubstrate in the structure shown in FIG. 2 is considered. The smallerthe potential in the substrate created by the charges as describedabove, the greater the mobility of the carriers moving in thesemiconductor substrate, thereby improving mobility. Considering thedependency on ε₂ in Expression (7), it can be understood that Expression(7) becomes a maximum value in the case of ε₂=(ε₁×ε₃)^(1/2), anddecreases when ε₂ is either higher or lower than that value.Accordingly, it can be understood that the case where the dielectricconstant of the second insulator film, counting from the semiconductorsubstrate, is equivalent to the square root of the product of thedielectric constant of the closest insulator film to the semiconductorsubstrate and the dielectric constant of the third insulator filmcounting from the semiconductor substrate is most undesirable. Furtherthe case where ε₂ is either higher or lower than the value of(ε₁×ε3)^(1/2) is preferred. However, if the dielectric constant of thesecond insulator film counting from the semiconductor substrate is settoo low, undesirable results develop: such that the capacitive couplingbetween the channel region and the gate electrode weakens. Thus, thecontrollability of the gate electrode with respect to the potential ofthe channel region deteriorates, an adverse influence of the shortchannel effect increases, and device current driving capability isreduced. Accordingly, the dielectric constant of the second insulatorfilm, counting from the semiconductor substrate, is preferably set to ahigher value than the square root of the product of the dielectricconstants of the closest insulator film to the semiconductor substrateand the third insulator film, counting from the semiconductor substrate.Next, the potential in the semiconductor brought about by a charge Q3existing in the second insulator film, counting from the semiconductorsubstrate, and a charge Q4 existing at the interface between the closestinsulator film to the semiconductor substrate and the second insulatorfilm, counting from the semiconductor substrate, are considered. Thepotential is proportionate to(2ε_(Si)/(ε_(Si)+ε₁))×(2 ε₁/(ε₁+ε₂))  (8)when referencing Expression (6) and the description thereafter.Reduction in the value of Expression (8) by adjusting the dielectricconstant of the second insulator film, counting from the semiconductorsubstrate, is considered. As described above, the smaller the potentialdue to the charges in the gate insulator film, the greater the mobilityof the carriers moving in the semiconductor substrate, so as to improvemobility. The value of Expression (8) decreases as E 2 increases.Accordingly, it can be understood that a higher dielectric constant ofthe second insulator film counting from the semiconductor substrate, ismore desirable. It can be understood from the discussion relating toExpression (8) and Expression (7), given thereabove, that the dielectricconstant of the second insulator film counting from the semiconductorsubstrate is preferably set to a higher value than the square root ofthe product of the dielectric constants of the closest insulator film tothe semiconductor substrate and the third insulator film, counting fromthe semiconductor substrate. Here, the gate insulator film of thecomparative example as shown in FIG. 125 is considered. Since the gateinsulator film in this case is made up of two stacked layers of a metaloxide and silicon oxide, the case of ε₂=ε₃ may be considered withExpressions (7) and (8). Since the insulator film closest to thesemiconductor substrate is assumed to be silicon oxide, silicon nitride,or oxidized and nitrided silicon as described before Expression (7), andthe third insulator film side is assumed to be an insulator film of ahigh dielectric material such as a metal oxide, the relationship ε₁<ε₃can be expected to be established. Accordingly, when ε₂=ε₃,ε₂>(ε₁×ε₃)^(1/2) holds true, the value of Expression (2) is a maximumvalue, and decreases if ε₂ is greater than the value ε₂=(ε₁×ε₃)^(1/2).Therefore, assuming that ε₂>ε₃ in a gate insulator film with at leastthree layers as shown in FIG. 2, it can be understood that the potentialin the semiconductor substrate due to the charge Q1 or Q2 is smallerthan in the case of the gate insulator film of the comparative exampleas shown in FIG. 125. Furthermore, since the value of Expression (8)decreases as E 2 increases, assuming that ε₂>ε₃ in a gate insulator filmwith at least three layers as shown in FIG. 2, it can be understood thatthe potential in the semiconductor substrate due to Q3 or Q4 is smallerthan in the case of the gate insulator film of the comparative exampleas shown in FIG. 125. Therefore, assuming that ε₂>ε₃ in a gate insulatorfilm with at least three layers as shown in FIG. 2, it can be understoodthat the potential in the semiconductor substrate due to charges otherthan those at the interface between the semiconductor substrate and theclosest insulator film to the semiconductor substrate, which is asilicon oxide, a silicon nitride, or an oxidized and nitrided siliconinsulator film, is smaller than in the case of the gate insulator filmof the comparative example as shown in FIG. 125. Furthermore, there isvery little charge at the interface between the semiconductor substrateand the closest insulator film to the semiconductor substrate.Therefore, assuming that ε₂>ε₃ in a three-layered gate insulator film asshown in FIG. 2, it can be understood that the mobility of the carriersmoving in the semiconductor substrate increases more than in the case ofthe gate insulator film of the comparative example as shown in FIG. 125.Furthermore, ε₂ is set extremely high in the three-layered gateinsulator film structure. Thus, controllability of the gate electrodewith respect to the potential in the channel region may be notsubstantially affected due to provision of such insulator film layers.As a result, the short channel effect may be controlled and high currentdriving capability may be implemented. It should be noted that thesecond and the third insulator film, counting from the semiconductorsubstrate, are depicted with nearly equal thicknesses; however,thickness is not of essence to the present description.

Next, a gate insulator film with at least two layers as shown in FIG. 3is considered. An insulator film made of a high dielectric material suchas a metal oxide is assumed as the second insulator film counting fromthe semiconductor substrate. The gate insulator film in thesemiconductor device of the comparative example as shown in FIG. 125 isprovided by making the closest insulator film to the semiconductorsubstrate of silicon oxide, silicon nitride or oxidized and nitridedsilicon. To begin with, the potential in the semiconductor due to acharge Q5 existing in the second insulator film counting from thesemiconductor substrate and a charge Q6 existing at the interfacebetween the second insulator film counting from the semiconductorsubstrate and the closest insulator film to the semiconductor substrateis considered. This potential is proportional to(2ε_(Si)/(ε_(Si)+ε₁))×(2ε₁/(ε₁+ε₂))  (9)when referencing Expression (6) and as described thereafter. Reductionin the value of Expression (9) by adjusting the dielectric constant ofthe closest insulator film to the semiconductor substrate in thestructure shown in FIG. 3 is considered. As described above, the smallerthe potential in the gate insulator film due to the charges, the greaterthe mobility of the carriers moving in the semiconductor substrate,thereby improving mobility. Considering the dependency on ε₁ inExpression (9), it can be understood that the value of Expression (9) isa maximum value in the case of ε₁=(ε_(Si)×ε₂)^(1/2), and decreases whenε₁ is either higher or lower than that value. Therefore, it can beunderstood that the case where the dielectric constant of the closestinsulator film to the semiconductor substrate is equivalent to thesquare root of the product of the dielectric constant of thesemiconductor substrate and the dielectric constant of the secondinsulator film, counting from the semiconductor substrate, is mostundesirable. Further the case where such dielectric constant is eitherhigher or lower is preferred. However, if the dielectric constant of theclosest insulator film to the semiconductor substrate is set too low,the capacitive coupling between the channel region and the gateelectrode weakens. This weakened capacitive coupling causes undesirableresults to develop: such as weakening of the controllability of the gateelectrode with respect to the potential of the channel region, anadverse influence of the short channel effect increases, and devicecurrent driving capability is reduced. Therefore, the dielectricconstant of the closest insulator film to the semiconductor substrate ispreferably set to a higher value than the square root of the product ofthe dielectric constants of the semiconductor substrate and the secondinsulator film, counting from the semiconductor substrate. Next, thepotential in the semiconductor due to a charge Q7 existing in theclosest insulator film to the semiconductor substrate and a charge Q8existing at the interface between the closest insulator film to thesemiconductor substrate and the semiconductor substrate is considered.This potential is proportionate to(2ε_(Si)/(ε_(Si)+ε₁))  (10)when referencing Expression (6) and the description thereafter.Reduction in the value of Expression (10) by adjusting the dielectricconstant of the closest insulator film to the semiconductor substrate isconsidered. As described above, the smaller the potential in the gateinsulator film due to the charges, the greater the mobility of thecarriers moving in the semiconductor substrate, thereby improvingmobility. The value of Expression (10) decreases as ε₁ increases.Therefore, it can be understood that the higher the dielectric constantof the closest insulator film to the semiconductor substrate, the morepreferable. It can be understood from the discussion relating toExpression (10) and Expression (9), given thereabove, that thedielectric constant of the closest insulator film to the semiconductorsubstrate is preferably set to a higher value than the square root ofthe product of the dielectric constants of the semiconductor substrateand the second insulator film, counting from the semiconductorsubstrate. Here, the gate insulator film of the comparative example asshown in FIG. 124 is considered. Since the gate insulator film of thepresent case is made up of a single layer of a metal oxide, the case ofε₁=ε₂ may be considered with Expression (9) or (10). Since the secondinsulator film, counting from the semiconductor substrate, is assumed tobe a metal oxide as described before Expression (9), ε₂ may be assumedto be approximately the same as or higher than the dielectric constantof the silicon forming the semiconductor substrate. Accordingly, it canbe understood that an inequality relationship ε₁>(ε_(Si)×ε₂)^(1/2) holdstrue, when ε₁=ε₂. As described above, since the value of Expression (9)is a maximum value when ε₁=(ε_(si)×ε₂)^(1/2), and decreases if ε₁ isgreater than the value (ε_(si)×ε₂)^(1/2), assuming that ε₁>ε₂ in a gateinsulator film with at least two layers as shown in FIG. 3, it can beunderstood that the potential in the semiconductor substrate due to Q5or Q6 is smaller than in the case of the gate insulator film of thecomparative example as shown in FIG. 124. Furthermore, since the valueof Expression (10) decreases as ε₁ increases, assuming that ε₁>ε₂ in agate insulator film with at least two layers as shown in FIG. 3, it canbe understood that the potential in the semiconductor substrate due toQ7 or Q8 is smaller than in the case of the gate insulator film of thecomparative example as shown in FIG. 124. Therefore, assuming that ε₁>ε₂in a gate insulator film with two layers as shown in FIG. 1, it can beunderstood that the potential in the semiconductor substrate due to thecharges in the gate insulator film or at the interface between the gateinsulator film and the semiconductor substrate is smaller than in thecase of the gate insulator film of the comparative example as shown inFIG. 124. Therefore, assuming that ε₁>ε₂ in a two-layered gate insulatorfilm as shown in FIG. 3, it can be understood that the mobility of thecarriers moving in the semiconductor substrate increases more than inthe case of the gate insulator film of the comparative example as shownin FIG. 124. Furthermore, since ε₁ is set extremely high in thisstructure compared to the dielectric constant of silicon oxide, siliconnitride or oxidized and nitrided silicon, controllability of the gateelectrode with respect to the potential in the channel region may befairly small due to provision of such insulator film layers.Particularly, compared to when an insulator film made of silicon oxide,silicon nitride, or oxidized and nitrided silicon is provided betweenthe insulator film, which is made of a metal oxide or the like, and thesemiconductor substrate as shown in FIG. 125, controllability of thegate electrode with respect to the potential in the channel region maybe fairly large. As a result, the short channel effect may be controlledand high current driving capability may be implemented. It should benoted that in FIG. 3, the closest insulator film to the semiconductorsubstrate and the second insulator film, counting from the semiconductorsubstrate, are depicted with nearly equal thicknesses; however, suchequal thickness is not of essence to the present description.

It should be noted that each of Expressions (6) to (10) in thisdiscussion depends on only the ratio of mutual dielectric constants ofeach insulator film. Therefore, the larger the ratio of ε_(si) to ε₁, ε₁to ε₂, and ε₂ to ε₃ or the ratio of dielectric constants of neighboringinsulator film layers in the stacked gate insulator film as shown inFIG. 2 or 3, the more significant the effect of this embodiment.Accordingly, it is preferable that the insulator film to be set with ahigh dielectric constant as described above is made of a high dielectricmaterial such as a metal oxide, a silicate thereof, or a nitridethereof.

As such, the field-effect transistor according to this embodiment iscapable of operating at a high speed by enhancing the controllability ofthe gate electrode with respect to the potential in the channel regionusing a high dielectric material such as a metal oxide for the gateinsulator film, and thereby controlling the short channel effect andalso controlling scattering of carriers due to the charges in the gateinsulator film and at the interface between that gate insulator film andthe semiconductor substrate. Such structure and resultant operationincreases the mobility of the carriers moving in the semiconductorsubstrate. Accordingly, a highly efficient, minute device capable ofhigh-speed operation may be provided.

FIG. 4 is a cross section of the field-effect transistor of thisembodiment. An n-channel field-effect transistor is taken as an examplein this embodiment. The identical effects may be obtained as in the caseof the p-channel field-effect transistor if the impurity conductivitytype is reversed, and also as in the case of a complementaryfield-effect semiconductor using a method of implanting an impurity onlyin a specified region in the substrate through a method such asphoto-lithography-process.

This field-effect transistor is characteristic of a gate insulator filmwith a three-layer stacked structure. The closest layer to asemiconductor substrate 1 is formed of a silicon oxide film 10, siliconnitride, or oxidized and nitrided silicon, the second and the thirdlayer counting from the semiconductor substrate 1 are gate insulatorfilms 11 and 5 made of a metal oxide, and the dielectric constant of thegate insulator film, which is the second layer counting from thesemiconductor substrate, is higher than that of the gate insulator film5, which is the third layer. This field-effect transistor is structuredsuch that a gate insulator film is formed of stacked films including anadditional high dielectric layer between two stacked layers of the gateinsulator film in the field-effect transistor of the comparative exampleshown in FIG. 125, more specifically, between the insulator film made ofa metal oxide or the like and the insulator film made of the siliconoxide film 10, silicon nitride, or oxidized and nitrided silicon. Suchconfigured gate insulator film has the same structure as the stackedfilms in FIG. 2. Thereby, in accordance with the reasons describedreferencing FIG. 2, carrier mobility increases by controlling scatteringof the carriers moving in the semiconductor substrate due to the chargesin the gate insulator film. Therefore, a higher current drivingcapability than with the semiconductor device in the structure of thecomparative example shown in FIGS. 124 and 125 may be provided. As aresult, using a high dielectric material such as a metal oxide for thegate insulator film, controllability of the gate electrode with respectto the potential in the channel region may be improved and high mobilitymay be implemented. Further a highly efficient, minute semiconductordevice capable of high-speed operation may be implemented.

This field-effect transistor further includes device isolation regions 2formed on the p-type silicon substrate 1 through trench deviceisolation. The p-well region 3 is formed in the p-type silicon substrate1, and the n-channel region 4 is formed in the p-well region 3. A gateinsulator film 12, which has a stacked structure of an insulator film 10made of the silicon oxide film, silicon nitride or oxidized and nitridedsilicon, the gate insulator film 5 made of a metal oxide or the like,and the gate insulator film 11 made of a metal oxide with a higherdielectric constant than the gate insulator film 5, are formed on then-channel region 4; and a gate electrode 6 is formed upon the stackedgate insulator film 12. Reference numeral 7 denotes source/drain region,8 denotes interconnects, and 9 denotes inter-layer insulator films.

Next, a fabrication method for this field-effect transistor is describedforthwith.

To begin with, as shown in FIG. 5, for example, the device isolationregions 2 are formed on the p-type Si substrate 1 through shallow trenchisolation. B ions, for example, are implanted in a p-well formationregion using an acceleration energy V_(acc)=100 keV with a dosageΦ=2.0×10¹³ ions/cm², and then forming a p-well region 3 by thermaltreatment at 1050° C. for 30 seconds, for example.

As shown in FIG. 6, for example, B ions are implanted into the p-wellregion 3 using an acceleration energy V_(acc)=30 keV with a dosageΦ=1.0×10¹³ ions/cm² and the value of the surface impurity concentrationof the n-channel region 4 is adjusted in order to obtain a desiredthreshold voltage.

As shown in FIG. 7, the 1 nm-thick silicon oxide film 10, for example,is formed using a method such as exposing the film to a heated oxygengas, for example.

As shown in FIG. 8, the gate insulator film 11 made of a 3 nm-thick TiO₂film, for example, is formed by sputtering or related methods.

As shown in FIG. 9, the gate insulator film 5 made of a 5 nm-thick HfO₂film, for example, is formed by sputtering, or related methods.

As shown in FIG. 10, for example, a refractory metal film such astungsten with a thickness of 100 nm is deposited on the HfO₂ film 5through CVD, and the gate electrode 6 is then formed by processing therefractory metal film through anisotropic etching such as RIE (ReactiveIon Etching) or the like. Subsequently, the gate insulator film 5 madeof an HfO₂ film, the gate insulator film 11 made of a TiO₂ film, and thestacked gate insulator film 12 made of the silicon oxide film 10 areprocessed through anisotropic etching.

As shown in FIG. 11, arsenic (As) ions are implanted using anacceleration energy V_(acc)=50 keV with a dosage Φ=5.0×10¹⁶ ions/cm²,for example. The source/drain region 7 is then formed through thermaltreatment.

Subsequently, as shown in FIG. 12, a silicon oxide film is deposited asthe interlayer insulator films 9 to a depth of 500 nm through CVD(Chemical Vapor Deposition) or the like, and interconnect openings 13are then formed on the source/drain regions 7 and the gate electrode 6through RIE or the like.

A 300 nm-thick Al film, for example, containing 1% Si is then formedacross the entire surface of the Si substrate 1 through sputtering orthe like. Subjecting this Al film to anisotropic etching allowsformation of the interconnects 8, forming the field-effect transistor ofthe embodiment shown in FIG. 4.

The n channel field-effect transistor has been taken as an example inthis embodiment; however, usage of an opposite conductivity type ofimpurity allows usage of this invention for a p channel field-effecttransistor. Moreover, implanting an impurity only in a specified regionin the substrate through a method such as photo etching allows usage ofthe invention for a complementary field-effect transistor. Furthermore,the techniques as described above may be used for a semiconductorapparatus including the n channel field-effect transistor, the p channelfield-effect transistor and the complementary field-effect transistorsas a part thereof.

Additionally, the techniques can be used to form field-effecttransistors as a part of a semiconductor including elements other thanthe field-effect transistor, a different active device such as a bipolartransistor or a single-electron transistor, a passive device such as aresistive element, a diode, an inductor or a capacitor, or an elementconfigured of a ferroelectric or an element made of a magnetic material.Similarly, even in the case of forming field-effect transistors as apart of an opto-electronic integrated circuit (OEIC) or amicro-electromechanical system (MEMS), the same techniques can be used.Furthermore, the same holds for a device with a silicon on insulator(SOI) structure and a FIN-type or columnar structured device.

In the present embodiment, As is used as an impurity for forming then-type semiconductor layer, and B is used as an impurity for forming thep-type semiconductor layer. Alternatively, a different group V impuritymay be used for forming the n-type semiconductor layer, and a differentgroup III impurity may be used for forming the p-type semiconductorlayer. Moreover, introduction of group III or group V impurities may beperformed using a compound containing both such impurities.

With the present embodiment, introduction of an impurity is performedthrough ion implantation; however, a method other than ion implantationsuch as solid phase diffusion or vapor phase diffusion may be used.Moreover, a deposition and a growth method for a semiconductorcontaining impurities may also be used.

In the present this embodiment, a device with a single drain structureis described; however, a device with a structure other than a singledrain structure such as an extension structure, a lightly doped drain(LDD) structure or a graded doped drain (GDD) structure may beconstructed. Moreover, a device with a halo structure, a pocketstructure or an elevated structure may be used.

In the present embodiment, formation of the source/drain regions isperformed after the gate electrode and the gate insulator film areprocessed; however, the order thereof is not essential, and may beperformed in the reverse order. There are cases where thermal treatmentis not preferable depending on the material of the gate electrode andthe gate insulator film. In such case, introduction of an impurity intoa source/drain region to be performed prior to processing of the gateelectrode and the gate insulator film is preferred.

In the present embodiment, formation of metallic layers forinterconnects is performed through sputtering; however, the metalliclayers may be formed using a different method other than sputtering,such as deposition. Furthermore, a method such as selective growth of ametal or damascene may be used. Moreover, the metallic material forinterconnects does not need to be aluminum (Al) containing Si, and adifferent metal such as copper (Cu) may be used instead. Cu isappropriate especially since it has low resistivity.

Furthermore, in the embodiment, the gate electrode is made of arefractory metal; however, the gate electrode may be made of asemiconductor such as a polycrystalline silicon, monocrystalline siliconor amorphous silicon, a metal other than a refractory type, a compoundcontaining a metal, or stacked layers thereof. Gate resistance iscontrolled by forming a gate electrode with a metal or a compoundcontaining a metal so that a device can operate at a high speed, whichis favorable.

In the embodiment, a silicide process is not mentioned; however, asilicide layer may be formed on the source and the drain region.Moreover, a method of depositing or growing a layer containing a metalon the source and the drain region may also be used. In this way, theresistance of the source and the drain region may be favorably reduced.Furthermore, in the case of forming the gate electrode with apolycrystalline silicon, the gate electrode or a part thereof may beprocessed to have a silicide layer. When a silicide layer is formed, thegate resistance is favorably reduced.

In the embodiment, the upper portion of the gate electrode has astructure exposing the electrode; however, an insulating material suchas silicon oxide, silicon nitride or oxidized and nitrided silicon maybe provided on that upper portion. This is particularly true in the casewhere the gate electrode is made of a material containing a metal and asilicide layer is formed on the source and the drain region. This isalso true in the case where protecting the gate electrode during thefabrication process is necessary, in which a protective material such assilicon oxide, silicon nitride or oxidized and nitrided silicon needs tobe provided on the upper portion of the gate electrode.

In the embodiment, gate sidewalls are not mentioned; however, sidewallsmay be provided to the gate electrode. Providing gate sidewalls made ofa high dielectric material is particularly favorable since the electricfield within the gate insulator film in the vicinity of the gateelectrode lower edge is weakened, providing an advantage of improvementin the reliability of the gate insulator film.

In the embodiment, formation of the gate electrode is performed througha method of depositing a gate electrode material and then subjecting thegate electrode material to anisotropic etching. However, the gateelectrode may be formed through a method of embedding or the like suchas the damascene process. In the case of forming the source and thedrain region prior to formation of the gate electrode, employing thedamascene process is preferred since the source and the drain region andthe gate electrode are formed in a self-aligning manner.

In the embodiment, the lengths of the upper and lower portion of thegate electrode along the main component of current flowing through thedevice are equal; however, this is not essential. For example, the gateelectrode may have a T-shape where the length along the upper portion ofthe gate electrode is longer than the lower portion. Another advantageof reduction in the gate resistance may also be obtained in this case.

In the embodiment, a silicon oxide film, which is formed by beingexposed to a heated oxygen gas, is used as the closest insulator film tothe semiconductor among the insulator films forming the gate insulatorfilm. However, the insulator film may be made of silicon nitride oroxidized and nitrided silicon, for example. However, since few chargesor few impurity energy levels existing in the insulator film or at theinterface between the insulator film and the semiconductor substrate arefavorable, usage of silicon oxide in light of this situation ispreferred. On the other hand, from the viewpoint of preventing diffusionof an impurity in the channel region when using a semiconductor as thegate electrode, usage of silicon nitride or oxidized and nitridedsilicon is preferred since they are known to allow control of impuritydiffusion due to existence of nitrogen. Furthermore, the fabricationmethod is not limited to heated oxygen gas exposure, and deposition, forexample, may be used, and exposure to an excited oxide gas without anincrease in temperature may be performed. Formation by a method ofexposing to an excited oxygen gas without an increase in temperatureallows control of changes in impurity concentration distribution withinthe channel regions due to diffusion, and is thus appropriate.Furthermore, in the case of using oxidized and nitrided silicon, first,the silicon oxide film is formed, and subsequently nitrogen may beintroduced in the insulator film by exposing that formed film to a gascontaining nitrogen with an increased temperature or excited nitrogen.

In the embodiment, a TiO₂ film, which is formed through sputtering asthe second insulator film counting from the semiconductor substrateamong the insulator films forming the gate insulator film, is used;however, a different high dielectric film may be used such as aninsulator film containing an oxide of a valence of Ti, BaO, BaTiO₃,BaWO₄, BaZnGeO₄, Bi₁₂GeO₂₀, Bi₁₂SiO₂₀, Bi₁₂TiO₂₀, CaMoO₄, CaYAlO₄,Dy₂Ti₂O₇, EuAlO₃, Eu₃NbO₇, EuO, Gd₃NbO₇, Ho₂Ti₂O₇, LaAlO₃, La₂Be₂O₅,La₂CuO₄, LaTi₂O₇, LiNbO₃, LiTaO₃, MnO, Nb₂O₅, NdAlO₃, Nd₂Ti₂O₇, PbF₂,Pb₅GeV₂O₁₂, PbMoO₄, PbO, PbWO₄, PrAlO₃, SrMoO₄, SrTiO₃, SrWO₄, Ta₂O₅,TeO₂, UO₂, Yb₂Ti₂O₇, an oxide of a valence of a metal, or any one ofthese added with nitrogen. As is described with reference to FIG. 2, asufficiently high dielectric constant, particularly a higher dielectricconstant than the square root of the product of the dielectric constantsof the closest insulator film to the semiconductor substrate and thethird insulator film counting from the semiconductor substrate isessential for the second insulator film, counting from the semiconductorsubstrate. Therefore, this embodiment does not prove fully effectivewhen using a closest insulating film to the substance with a lowdielectric constant such as silicon nitride or oxidized and nitridedsilicon as the second insulator film. Furthermore, the fabricationmethod for the insulator film is not limited to sputtering, and adifferent method may be employed such as vapor deposition,chemical-vapor deposition (CVD), or epitaxial growth. Moreover, in acase such as using an oxide of a certain substance as the insulatorfilm, a method such as forming a film made of that substance and thenoxidizing the film may be employed.

In the embodiment, a hafnium oxide film (HfO₂ film) formed throughsputtering is used as the third insulator film, counting from thesemiconductor substrate, from among the insulator films forming the gateinsulator film. However, a different high dielectric film may be used asthe gate insulator film such as an insulator film containing an oxide ofa valence of hafnium (Hf), an oxide of a different metal such aszirconium (Zr), titanium (Ti), scandium (Sc), yttrium (Y), tantalum(Ta), Al, lanthanum (La), cerium (Ce), praseodymium (Pr) or an elementfrom the lanthanoid group, a silicate material containing variouselements including these and other elements, or any one of these addedwith nitrogen, or a different insulator film made of stacked layersthereof. When nitrogen exists in the insulator film, only a certainelement being crystallized and then precipitated may be controlled. Itshould be noted that this embodiment is established for reducingscattering of carriers due to the charges existing in the thirdinsulator film, counting from the semiconductor substrate, or at theinterface between the third and the second insulator film, counting fromthe semiconductor substrate. Therefore, the effects of this embodimentare significant when there are abundant charges such as in the case ofusing a metal oxide as the third insulator film. Furthermore, thefabrication method for the insulator film is not limited to sputtering,and a different method may be employed such as vapor deposition, CVD, orepitaxial growth. Moreover, in a case such as using an oxide of acertain substance as the insulator film, a method such as forming a filmmade of that substance and then oxidizing the film may be employed.

Furthermore, the thickness of each insulator film forming the gateinsulator film is not limited to the value of the thickness of eachinsulator film in this embodiment.

As is described for the above Expression 6, the potential within thesemiconductor substrate brought about by the point charges in thestacked insulator film as shown in FIGS. 1 through 3 is represented bythe power series exp(−kT_(j)) (T_(j) denotes the thickness of the j-thlayer from the semiconductor substrate.) and k denotes the wavenumberfor the potential subjected to the Fourier transform along the in-planeof the insulator film. Considering actual scattering of carriers,contribution of the Fermi wavenumber when assuming the carriers in aninversion layer are two-dimensional gas is large. To exactly approximatethe value of the potential in the semiconductor substrate based on theprimary term of the power series such as Expression (6), the value ofeach exp(−kT_(j)) must be appropriately small.

Accordingly, it is preferable that the thickness of an insulator filmlayer should be comparable to the Fermi wavelength/2π (=1/Fermiwavenumber) or greater when the carriers in the inversion layer areconsidered as a two-dimensional gas. Assuming the carriers in theinversion layer as two-dimensional ideal Fermi gas, and given thatN_(inv) denotes the carrier area density within the inversion layer, theFermi wavelength/2π is given by (πN_(inv))^(−1/2). In addition, giventhat T denotes the thickness of the gate insulator film when the film ismade of an oxide film (SiO₂film thickness allowing formation of anelectrical capacitance equal to that of a parallel flat plate capacitorwith the same insulator film as the gate insulator film using a parallelflat plate capacitor), and V₀ denotes a difference between the powersupply voltage and the threshold voltage, N_(inv) when a typical deviceis in an on-state is given by ε_(si)V₀/T. Therefore, assuming T=1 nm andV₀=1V, which are expected in the generation of several 10 nm long gates,the area density of the carriers in the inversion layer while thetypical device is in an on-state is N_(inv)=2×10³ cm⁻² and the Fermiwavelength/2π is 1.2 nm. It should be noted that geometrically speaking‘insulator film thickness’ in this case is a film thickness. Thus, thefilm thickness being 1.2 nm or greater is consistent with the filmthickness in an oxide film thickness equivalent to approximately 1 nm.

Accordingly, the thickness of each insulator film layer is preferablyapproximately 1.2 nm or greater. Furthermore, when the thickness of eachinsulator film layer is equal to or greater than the product of theFermi wavelength and the natural logarithm of 10, each value ofexp(−kT_(j)) is equal to {fraction (1/10)} or less, namely a smallerorder of magnitude than the terms not including this exponentialfunction, is more favorable to provide a minute semiconductor devicecapable of high-speed operations by reducing the scattering of carriersas well as enhancing the controllability of the gate electrode withrespect to the potential of the channel region. Accordingly, it is evenmore favorable when the thickness of each insulator film layer isapproximately 2.8 nm or greater. However, in the case of using asubstance with a low dielectric constant such as silicon oxide, siliconnitride or oxidized and nitrided silicon as the closest insulator filmto the semiconductor substrate, since the electrical capacitance betweenthe channel region and the gate electrode is reduced when that thicknessis too thick compared to the value 2.8 nm, controllability of the gateelectrode with respect to the potential of the channel region isreduced, which is not favorable to provide a minute semiconductor devicecapable of high-speed operations by reducing the scattering of carriersas well as enhancing the controllability of the gate electrode withrespect to the potential of the channel region. Accordingly, especiallywith the stacked structure as shown in FIG. 2, it is preferable thatthickness of the second or the third insulator film, counting from thesemiconductor substrate, is 1.2 nm or greater, even further preferableif it is 2.8 nm or greater.

The present embodiment was devised for reducing scattering of carriersin the semiconductor substrate due to the charges existing in the thirdinsulator film counting from the semiconductor substrate, in a device,using a high dielectric material such as a metal oxide for the gateinsulator film, wherein a new insulator film layer is provided to thegate insulator film. Reduction in scattering of the carriers due to thecharges in the gate insulator film and the like is important. However,considering an increase in the short channel effect and reduction incurrent driving capability, reduction in the controllability of the gateelectrode with respect to the potential of the channel region is notfavorable to provide a minute semiconductor device capable of high-speedoperations by reducing the scattering of carriers as well as enhancingthe controllability of the gate electrode with respect to the potentialof the channel region. Accordingly, with the structure of the embodimentshown in FIG. 4, it is preferable that the thickness of the secondinsulator film, counting from the semiconductor substrate, which is theessential difference from the comparative example shown in FIG. 125, isnot very thick. However, the essential value is not the insulator filmthickness geometrically speaking when considering the controllability ofthe gate electrode with respect to the potential of the channel region,but is a value derived by dividing the insulator film thickness by itsdielectric constant. Accordingly, it is preferable that the valuederived by dividing the thickness of the second insulator film, countingfrom the semiconductor substrate, by its dielectric constant is smallerthan the value derived by dividing the thickness of the third insulatorfilm, counting from the semiconductor substrate, by its dielectricconstant.

In the embodiment, the gate insulator film has a three-layer stackedstructure; however, if the relationship between dielectric constant andthickness as described above is satisfied, a gate insulator film with astacked structure of four or more layers may be formed.

In the embodiment, device isolation is performed through shallow trenchisolation; however, a different method such as local oxidation or mesadevice isolation may be used.

In the embodiment, post-oxidation after the gate electrode has beenformed is not mentioned; however, a post oxidation process may beperformed if possible in light of the gate electrode and gate insulatorfilm materials. Moreover, not limited to post-oxidation, rounding thegate electrode lower edge may be performed through a method such aschemical processing or exposure to a reactive gas. When these processesare possible, the electric field at the gate electrode lower edge isrelaxed therethrough.

In the embodiment, a silicon oxide film is used as the interlayerinsulator film. However, a substance other than silicon oxide such as alow dielectric material may be used for the interlayer insulator film.Lowering the dielectric constant of the interlayer insulator film allowsreduction in device parasitic capacitance, thereby providing anadvantage of achieving high-speed operations of the device.

Furthermore, with regard to contact holes, self-aligned contacts may beformed. The device area may be reduced using self-aligned contacts,thereby improving the scale of integration.

In the embodiment, the case of a semiconductor device with only a singlelayer of interconnect is described; however, devices and/orinterconnects may be made of two or more layers. The degree of deviceintegration increases in that case.

In the embodiment, the gate insulator film is removed from the sourceand the drain region; however, it may be retained. For example, sincedose losses are prevented when forming the source and the drain regionthrough ion implantation after the gate electrode has been formed,removing the gate insulator film on the source and the drain region ispreferred. Furthermore, removal is necessary when forming a silicidelayer in the source and the drain region. Moreover, the removal methodis not limited to RIE, and a method such as CDE or wet processing may beemployed.

MODIFIED EXAMPLE OF THE FIRST EMBODIMENT

In the embodiment, sidewalls of the gate insulting film 12 with astacked structure as shown in FIG. 4 are processed, so as to match thegate electrode 6. However, the gate insulator film 12 with a stackedstructure as shown in FIGS. 13 through 19, for example, may beprocessed, so as to overhang from the gate electrode 6. By doing so, thecapacitive coupling between the source/drain regions 7 and the gateelectrode 6 is strengthened. Therefore, advantages of reducing theresistance of the source/drain regions 7, controlling the parasiticcapacitance as well as allowing high-speed operations are obtained.Furthermore, the gate insulator film 12 with a stacked structure asshown in FIGS. 20 through 26 may be processed, so as to be furtherinward than the gate electrode 6. By doing so, the electricalcapacitance to be formed between the gate electrode 6 and thesource/drain regions 7 decreases. Therefore, advantages of reducing theparasitic capacitance as well as allowing high-speed operations areobtained. Moreover, by processing the stacked gate insulator film 12 soas to be further inward than the gate electrode 6, an advantage of arelaxed electric field in the stacked gate insulator film 12 near thegate electrode 6 lower edge is obtained.

Furthermore, the length of the insulator film along the main componentof current flowing through the element does not need to vary inaccordance with the order from the semiconductor substrate 1, but mayhave a form as shown in FIGS. 27 through 36, for example. Moreover, thesidewalls of the stacked gate insulator film 12 need not beperpendicular to the semiconductor device surface, but may be slanted asshown in FIGS. 37 through 52. In addition, the sidewalls of the stackedgate insulator film 12 may be curved as shown in FIGS. 53 through 76,for example. Changing the form of the stacked gate insulator film 12near the gate electrode 6 lower edge changes the electrical capacitancebetween the gate electrode 6 and the source/drain regions 7. Theelectrical capacitance between the gate electrode 6 and the source/drainregions 7 is preferably large from the standpoint of controlling theparasitic resistance, which is caused by the resistance of thesource/drain regions 7, and is preferably small from the standpoint ofreducing the device parasitic capacitance. If the form of the stackedgate insulator film 12 near the gate electrode 6 lower edge is changedas in this modified example, the electrical capacitance between the gateelectrode 6 and the source/drain regions 7 may be adjusted, and thusthere is an advantage of optimization.

Furthermore, in the embodiment and modified example thereof, the form ofthe gate insulator film is made symmetrical with a source and a drainside; however, the source and the drain side may be asymmetrical.

Moreover, with the embodiment and modified example thereof, thethickness of each insulator film forming the stacked gate insulator film12 is even across the entire channel region. However, any of theinsulator films 10, 11 and 5, which form the stacked gate insulator film12 near the gate electrode 6, may be formed thicker without necessarilybeing even. In this case, since the electrical capacitance to be formedbetween the gate electrode 6 and the source/drain regions 7 decreases,there is an advantage of controlling the parasitic capacitance so thatthe devices operate at a higher speed. Furthermore, any of the insulatorfilms 10, 11 and 5, which form the stacked gate insulator film 12 nearthe gate electrode 6, may be formed thinner. In this case, since theresistance of the source/drain regions 7 is reduced and the parasiticcapacitance is controlled due to the strengthened capacitive couplingbetween the source/drain regions 7 and the gate electrode 6, there isthe advantage of achieving higher-speed operations.

It should be noted that a structure with only a single transistor isdescribed in the embodiment and modified example thereof; however, thisembodiment is not limited to the case of a single transistor.

With the semiconductor device according to the embodiment of the presentinvention, scattering of the carriers moving in the semiconductorsubstrate due to the charges existing in the gate insulator film or atthe interface between the gate insulator film and the semiconductorsubstrate may be controlled. Mobility of the carriers in the channel isimproved as a result. Furthermore, high controllability of the gateelectrode with respect to the potential of the channel region may beachieved. A highly efficient, minute device capable of high-speedoperation may be implemented as a result.

(Second Embodiment)

Next, a field-effect transistor of a second embodiment is describedwhile referencing FIGS. 77 through 79. FIG. 77 is a cross section of thefield-effect transistor of this embodiment. The field-effect transistorhas a two layer stacked gate insulator film, and each insulator film ismade of a metal oxide. The dielectric constant of the closest layer tothe semiconductor substrate is higher than that of the second layer,counting from the semiconductor substrate. The field-effect transistorhas a structure with a gate insulator film made of two layers as in thefield-effect transistor of the comparative example shown in FIG. 125,wherein one gate insulator film made of silicon oxide, silicon nitride,or oxidized and nitrided silicon is formed of an insulator film using ahigh dielectric material, such as a metal oxide. Such configured gateinsulator film has the same structure as the stacked films in FIG. 1,and according to the reasons described with reference to FIG. 3, carriermobility increases by controlling scattering of the carriers due to thecharges in the gate insulator film or at the interface between the gateinsulator film and the semiconductor substrate. Therefore, a highercurrent driving capability than with the semiconductor device with thestructure of the comparative example shown in FIGS. 124 and 125 may beobtained. Furthermore, as opposed to the closest insulator film to thesemiconductor substrate in the semiconductor device of the comparativeexample shown in FIG. 125 being made of silicon oxide, silicon nitride,or oxidized and nitrided silicon, the closest insulator film to thesemiconductor substrate in the semiconductor device shown in FIG. 77 ismade of a high dielectric material, such as a metal oxide. Accordingly,satisfactory controllability of the gate electrode with respect to thepotential of the channel region is achieved. As a result, using a highdielectric material such as a metal oxide for the gate insulator film,controllability of the gate electrode with respect to the potential inthe channel region may be improved, high mobility may be attained, and ahighly efficient, minute semiconductor device capable of high-speedoperation may be implemented.

This field-effect transistor further includes device isolation regions 2formed on the p-type Si substrate 1 through trench device isolation. Thep-well region 3 is formed in the p-type Si substrate 1, and then-channel region 4 is formed in the p-well region 3. A gate insulatorfilm 14, which has a stacked structure of the gate insulator film 5 madeof a metal oxide or the like and the gate insulator film 11 made of ametal oxide with a higher dielectric constant than the gate insulatorfilm 5, is formed on the n-channel region 4; and the gate electrode 6 isformed on the stacked gate insulator film 14. Reference numeral 7denotes source/drain regions, 8 denotes interconnects, and 9 denotesinter-layer insulator films.

This field-effect transistor may be formed in the following manner. Inthe formation process, after the process shown in FIG. 6 of the firstembodiment, as shown in FIG. 78, the gate insulator film 11, which ismade of a 3 nm-thick TiO₂ film, for example, is formed through a methodsuch as sputtering.

Next, as shown in FIG. 79, the gate insulator film 5, which is made of a5 nm-thick HfO₂ film, for example, is formed through a method such assputtering. Subsequent steps are the same as in the process shown afterFIG. 10 of the first embodiment.

Various modifications as described in the first embodiment are alsopossible with this embodiment, and the same effects may be obtained.Further with this embodiment, a TiO₂ film, which is formed throughsputtering as the closest insulator film to the semiconductor substrate1 among the insulator films forming the gate insulator film, is used.However, a different high dielectric film may be used such as aninsulator film containing an oxide of a valence of Ti, BaO, BaTiO₃,BaWO₄₁ BaZnGeO₄, Bi₁₂GeO₂₀, Bi₁₂SiO₂₀, Bi₁₂TiO₂₀, CaMoO₄, CaYAlO₄,Dy₂Ti₂O₇, EuAlO₃, Eu₃NbO₇, EuO, Gd₃NbO₇, Ho₂Ti₂O₇, LaAlO₃, La₂Be₂O₁,La₂CuO₄, LaTi₂O₇, LiNbO₃, LiTaO₃, MnO, Nb₂O₅, NdAlO₃, Nd₂Ti₂O₇, PbF₂,Pb₅GeV₂O₁₂, PbMoO₄, PbO, PbWO₄, PrAlO₃, SrMoO₄, SrTiO₃, SrWO₄, Ta₂O₅,TeO₂, UO₂, Yb₂Ti₂₀₇, an oxide with a valence of a metal, or any one ofthese added with nitrogen. As is described referencing FIG. 3, asufficiently high dielectric constant, particularly a higher dielectricconstant than the square root of the product of the dielectric constantsof the Si substrate 1 and the second insulator film counting from the Sisubstrate 1 is essential for the first insulator film counting from theSi substrate 1. Therefore, this embodiment does not prove fullyeffective when using a substance with a low dielectric constant such assilicon oxide, silicon nitride or oxidized and nitrided silicon as theclosest insulator film to the Si substrate 1. Furthermore, thefabrication method for the insulator film is not limited to sputtering,and a different method may be employed such as vapor deposition, CVD, orepitaxial growth. Moreover, in a case such as using an oxide of acertain substance as the insulator film, a method such as forming a filmmade of that substance and then oxidizing the film may be employed.

In this embodiment, an HfO₂ film formed through sputtering is used asthe second insulator film counting from the Si substrate 1 from amongthe insulator films forming the gate insulator film. However, adifferent high dielectric film may be used as the gate insulator filmsuch as an insulator film containing an oxide of a valence of Hf, anoxide of a different metal such as Zr, Ti, Sc, Y, Ta, Al, La, Ce, Pr oran element from the lanthanoid group, a silicate material containingvarious elements including these and other elements, or any one of theseelements with nitrogen added, or a different insulator film made ofstacked layers. When nitrogen exists in the insulator film, only acertain element being crystallized and then precipitated may becontrolled. It should be noted that this embodiment was devised forreducing scattering of carriers due to the charges existing in the gateinsulator film, or at the interface between the gate insulator film andthe Si substrate. Accordingly, the effects of this embodiment aresignificant when there are abundant charges such as in the case of usinga metal oxide as the gate insulator film. Furthermore, the fabricationmethod for the insulator film is not limited to sputtering, and adifferent method may be used such as vapor deposition, CVD, or epitaxialgrowth. Moreover, in a case such as using an oxide of a certainsubstance as the insulator film, a method such as forming a film made ofthat substance and then oxidizing it may be employed.

Furthermore, the thickness of each insulator film forming the gateinsulator film is not limited in this embodiment. As is described forthe above Expression 6, the potential within the Si substrate due to thepoint charges in the stacked insulator film as shown in FIGS. 1 through3 is represented by the power series exp(−kT_(j)) (T_(j)denotes thethickness of the j-th layer from the Si substrate.) and k denotes thewavenumber for the potential subjected to the Fourier transform alongthe in-plane of the insulator film. Considering actual scattering ofcarriers, contribution of the Fermi wavenumber when assuming thecarriers in an inversion layer as two-dimensional gas is large. Toapproximate the value of the potential in the Si substrate using theprimary term of the power series such as in Expression (6), the value ofeach exp(−kT_(j)) must be appropriately small. Accordingly, it ispreferable that the thickness of an insulator film layer should becomparable to the Fermi wavelength or larger when assuming the carriersin the inversion layer as two-dimensional gas. Assuming that the areadensity of the carriers in the inversion layer is 2×10¹³ cm², which isapproximately the same as the area density of the carriers in theinversion layer in a typical device that is in an on-state, and that thecarriers in the inversion layer are a two-dimensional ideal Fermi gas,the Fermi wavelength is approximately 1.2 nm. Accordingly, the thicknessof each insulator film layer is preferably approximately 1.2 nm orgreater. Furthermore, when the thickness of each insulator film layer isequal to or greater than the product of the Fermi wavelength and thenatural logarithm of 10, the value of each exp(−kT_(j)) is equal to{fraction (1/10)} or less, namely a smaller order of magnitude than theterms not including this exponential function. Accordingly, when thethickness of each insulator film layer is approximately 2.8 nm orgreater, it is even more favorable to provide a minute semiconductordevice capable of high-speed operations by reducing the scattering ofcarriers as well as enhancing the controllability of the gate electrodewith respect to the potential of the channel region.

This embodiment was devised for reducing scattering of carriers in thesemiconductor substrate due to the charges existing in the secondinsulator film counting from the semiconductor substrate in a deviceusing a high dielectric material such as a metal oxide for the gateinsulator film. An additional insulator film layer is provided to thegate insulator film with the structure of the comparative example shownin FIG. 124. Reduction in scattering of the carriers due to the chargesin the gate insulator film and the like is important; however,considering an increase in the short channel effect and reduction incurrent driving capability, reduction in the controllability of the gateelectrode with respect to the potential of the channel region is notfavorable to provide a minute semiconductor device capable of high-speedoperations by reducing the scattering of carriers as well as enhancingthe controllability of the gate electrode with respect to the potentialof the channel region. Therefore, with the structure of this embodimentshown in FIG. 77, it is preferable that the thickness of the closestinsulator film to the semiconductor substrate, which is the essentialdifference from the comparative example shown in FIG. 124, is not verythick. However, the essential value is not the insulator film thickness,geometrically speaking, when considering the controllability of the gateelectrode with respect to the potential of the channel region, but is avalue derived by dividing the insulator film thickness by its dielectricconstant. Accordingly, it is preferable that the value derived bydividing the thickness of the closest insulator film to thesemiconductor substrate by its dielectric constant is smaller than thevalue derived by dividing the thickness of the second insulator filmcounting from the semiconductor substrate by its dielectric constant.

In this embodiment, the gate insulator film has a two-layer stackedstructure; however, if the relationship between dielectric constant andthickness as described above is satisfied, a gate insulator film with astacked structure of three or more layers may be formed.

MODIFIED EXAMPLE OF THE SECOND EMBODIMENT

With this embodiment, the sidewalls of the gate insulting film 14 withthe stacked structure as shown in FIG. 77 are processed so as to matchthe gate electrode 6; however, the gate insulator film 14 with thestructure as shown in FIGS. 80 through 82, for example, may be processedso as to overhang from the gate electrode 6. By doing so, the capacitivecoupling between the source/drain regions 7 and the gate electrode 6 isstrengthened, therefore advantages of reducing the resistance of thesource/drain regions 7, controlling the parasitic capacitance as well asallowing high-speed operations are obtained. Furthermore, the gateinsulator film 14 with the stacked structure as shown in FIGS. 83through 85 may be processed so as to be further inward than the gateelectrode 6. By doing so, the electrical capacitance to be formedbetween the gate electrode 6 and the source/drain regions 7 decreases,therefore advantages of reducing the parasitic capacitance as well asallowing high-speed operations are obtained. Moreover, by processing thestacked gate insulator film 14 so as to be further inward than the gateelectrode 6, an advantage of a relaxed electric field in the stackedgate insulator film 14 near the gate electrode 6 lower edge is obtained.

Furthermore, the length of the insulator film along the main componentof current flowing through the element does not need to vary inaccordance with the order from the semiconductor substrate 1, but mayhave a form as shown in FIGS. 86 through 91, for example. Moreover, thesidewalls of the gate insulator film need not be perpendicular to thesemiconductor device surface, but may be slanted as shown in FIGS. 92through 103. In addition, the sidewalls of the gate insulator film maycurve as shown in FIGS. 104 through 123, for example. Changing the formof the gate insulator film near the gate electrode 6 lower edge changesthe electrical capacitance between the gate electrode 6 and thesource/drain regions 7. The electrical capacitance between the gateelectrode 6 and the source/drain regions 7 is preferably large from thestandpoint of controlling the parasitic resistance, which is caused bythe resistance of the source/drain regions 7, and is preferably smallfrom the standpoint of reducing the device parasitic capacitance. If theform of the gate insulator film near the gate electrode 6 lower edge ischanged as in this modified example, the electrical capacitance betweenthe gate electrode 6 and the source/drain regions 7 may be adjusted, andthus there is an advantage of possible optimization to provide a minutesemiconductor device capable of high-speed operations by reducing thescattering of carriers as well as enhancing the controllability of thegate electrode with respect to the potential of the channel region.

With the semiconductor device according to this embodiment of thepresent invention, scattering of the carriers moving in thesemiconductor substrate due to the charges existing in the gateinsulator film or at the interface between the gate insulator film andthe semiconductor substrate may be controlled. Mobility of the carriersin the channel is improved as a result. Furthermore, highcontrollability of the gate electrode with respect to the potential ofthe channel region may be achieved. A highly efficient, minute devicecapable of high-speed operation may be implemented as a result.

(Other Embodiments)

While the present invention is described in accordance with theaforementioned embodiments, it should not be understood that thedescription and drawings that configure part of this disclosure are tolimit the present invention. This disclosure makes clear a variety ofalternative embodiments, working examples, and operational techniquesfor those skilled in the art. Accordingly, the technical scope of thepresent invention is defined by only the claims that appear appropriatefrom the above explanation.

Various modifications will become possible for those skilled in the artafter receiving the teachings of the present disclosure withoutdeparting from the scope thereof.

1. A semiconductor device, comprising: a semiconductor substrate; asource and a drain region arranged at the surface of the semiconductorsubstrate; a gate insulator film arranged on a channel defined betweenthe source and drain regions at the surface of the semiconductorsubstrate and implemented by a stacked structure including a firstinsulator film, a second insulator film containing a metal on the firstinsulator film, and a third insulator film containing a metal on thesecond insulator film; and a gate electrode arranged on the thirdinsulator film, wherein the dielectric constant of the second insulatorfilm is higher than the square root of the product of the dielectricconstants of the first and third insulator films.
 2. The semiconductordevice of claim 1, wherein the dielectric constant of the secondinsulator film is higher than that of the third insulator film.
 3. Thesemiconductor device of claim 1, wherein thicknesses of the secondinsulator film and the third insulator film are respectively greaterthan 1.2 nm.
 4. The semiconductor device of claim 1, wherein thicknessesof the second insulator film and the third insulator film arerespectively approximately 2.8 nm or greater than 2.8 nm.
 5. Thesemiconductor device of claim 1, wherein a value derived by dividing thethickness of the second insulator film by its dielectric constant issmaller than a value derived by dividing the thickness of the thirdinsulator film by its dielectric constant.
 6. The semiconductor deviceof claim 1, wherein the first insulator film is made of any one ofsilicon oxide, silicon nitride, or oxidized and nitrided silicon.
 7. Thesemiconductor device of claim 1, wherein the second insulator film ismade of any one of TiO₂, BaO, BaTiO₃, BaWO₄, BaZnGeO₄, Bi₁₂GeO₂₀,Bi₁₂SiO₂₀, Bi₁₂TiO₂₀, CaMoO₄, CaYAlO₄, Dy₂Ti₂O₇, EuAlO₃, Eu₃NbO₇, EuO,Gd₃NbO₇, Ho₂Ti₂O₇, LaAlO₃, La₂Be₂O₅, La₂CuO₄, LaTi₂O₇, LiNbO₃, LiTaO₃,MnO, Nb₂O₆, NdAlO₃, Nd₂Ti₂O₇, PbF₂, Pb₅GeV₂O₁₂, PbMoO₄, PbO, PbWO₄,PrAlO₃, SrMoO₄, SrTiO₃, SrWO₄, Ta₂O₅, TeO₂, UO₂, Yb₂Ti₂O₇.
 8. Thesemiconductor device of claim 1, wherein the second insulator film ismade of any one of oxide of a valence of Hf, an oxide of Zr, Ti, Sc, Y,Ta, Al, La, Ce, Pr or an element from the lanthanoid group, and asilicate material.
 9. The semiconductor device of claim 2, whereinthicknesses of the second insulator film and the third insulator filmare respectively greater than 1.2 nm.
 10. The semiconductor device ofclaim 2, wherein thicknesses of the second insulator film and the thirdinsulator film are respectively approximately 2.8 nm or greater than 2.8nm.
 11. The semiconductor device of claim 2, wherein a value derived bydividing the thickness of the second insulator film by its dielectricconstant is smaller than a value derived by dividing the thickness ofthe third insulator film by its dielectric constant.
 12. Thesemiconductor device of claim 2, wherein the first insulator film ismade of any one of silicon oxide, silicon nitride, or oxidized andnitrided silicon.
 13. A semiconductor device, comprising: asemiconductor substrate; a source and a drain region arranged at thesurface of the semiconductor substrate; a gate insulator film arrangedon a channel defined between the source and drain regions at the surfaceof the semiconductor substrate and implemented by a stacked structureincluding a first insulator film containing a metal and a secondinsulator film containing a metal on the first insulator film; and agate electrode arranged on the second insulator film, wherein thedielectric constant of the first insulator film is higher than thesquare root of the product of the dielectric constants of thesemiconductor substrate and the second insulator film.
 14. Thesemiconductor device of claim 13, wherein the dielectric constant of thefirst insulator film is higher than that of the second insulator film.15. The semiconductor device of claim 13, wherein thicknesses of thefirst insulator film and the second insulator film are respectivelygreater than 1.2 nm.
 16. The semiconductor device of claim 13, whereinthicknesses of the second insulator film and the third insulator filmare respectively approximately 2.8 nm or greater than 2.8 nm.
 17. Thesemiconductor device of claim 13, wherein a value derived by dividingthe thickness of the first insulator film by its dielectric constant issmaller than a value derived by dividing the thickness of the secondinsulator film by its dielectric constant.
 18. The semiconductor deviceof claim 13, wherein the first insulator film is made of any one ofsilicon oxide, silicon nitride, or oxidized and nitrided silicon. 19.The semiconductor device of claim 13, wherein the second insulator filmis made of any one of TiO₂, BaO, BaTiO₃, BaWO₄, BaZnGeO₄, Bi₁₂GeO₂₀,Bi₁₂SiO₂₀, Bi₁₂TiO₂₀, CaMoO₄, CaYAlO₄, Dy₂Ti₂O₇, EuAlO₃, Eu₃NbO₇, EuO,Gd₃NbO₇Ho₂Ti₂O₇, LaAlO₃, La₂Be₂O₆, La₂CuO₄, LaTi₂O₇, LiNbO₃, LiTaO₃,MnO, Nb₂O₅, NdAlO₃, Nd₂Ti₂O₇, PbF₂, Pb₅GeV₂O₁₂, PbMoO₄, PbO, PbWO₄,PrAlO₃, SrMoO₄, SrTiO₃, SrWO₄, Ta₂O₅, TeO₂, UO₂, Yb₂Ti₂O₇.
 20. Thesemiconductor device of claim 13, wherein the second insulator film ismade of any one of oxide of a valence of Hf, an oxide of Zr, Ti, Sc, Y,Ta, Al, La, Ce, Pr or an element from the lanthanoid group, and asilicate material.